LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity kongzhi is
port(xuanqu,clk:in std_logic;
     qu1,qu3,qu2,qingling1:out std_logic;
     xianshi:out std_logic_vector(3 downto 0));
end kongzhi;
ARCHITECTURE one of kongzhi is
signal kk:std_logic;
signal jin1:std_logic_vector(2 downto 0):="001";
begin
qingling1<=xuanqu;
kk<=xuanqu;
process(kk,jin1)
begin
if kk'event and kk='1' then 
if jin1<"011" then jin1<=jin1+1;else jin1<="001";
end if;
end if;
end process;
process(jin1,clk,xuanqu)
begin
case jin1 is
when "001"=>qu1<=clk;qu3<='0';qu2<='0';xianshi<="0001";
when "010"=>qu1<='0';qu3<='0';qu2<=clk;xianshi<="0010";
when "011"=>qu1<='0';qu2<='0';qu3<=clk;xianshi<="0011";
when others=>null;
end case;
end process;
end one;

